International Collaborative Partner of UTAR Global Research Network



Name Mr. Tang Chong Ming
Designation Consultant
Qualification M.Sc. (Computing), Imperial College of Sc & Tech, London, 1983.
M.Sc. (RADAR Scattering), University of Malaya, 1973.
B.Sc. Hons (Physics), University of Malaya, 1971.
Organization Universiti Sains Malaysia
Email cmtang.cm@gmail.com
Tel No. +65 9679 7989
UTAR Contact Person Dr. Tan Kia Hock, tankh@utar.edu.my


Employment
  • Vice President & General Manager, Digital Media Business Unit of Huahong Semiconductor International, Shanghai, an IDM initiative for the Chinese Government, 2006-2007.
  • Director, APAC & China Regions, R&D Centers, Agere Systems Singapore, Shanghai (nearly 100 R&D, Marketing, and System Application Engineering headcounts), 2002-2006.
  • Director, Regional, APAC R&D Centers, Agere Systems Singapore, Seoul, 2001-2002.
  • Director, Regional, Lucent Technologies, Bell Laboratories Design / R&D Centers Singapore, Tokyo, Taipei, Seoul. 1996-2001.
  • Director, Regional, Far East Design Centers, AT&T Bell Laboratories Singapore, Tokyo, Taipei, Seoul. 1990-1996.
  • Adjunct Associate Professor, Nanyang Technological University, School of IEEE, Singapore, 1986-2005.
  • Director, Regional, Far East Design Centers, AT&T Microelectronics Singapore, 1985-1990.
  • CAD Manager, ASIC Design Center, Honeywell Synertek, Singapore. 1984-1985.
  • Lecturer, Department of Physics, University of Malaya, Kuala Lumpur, 1973-1984.
Career Highlights
Design and Development
  • Pioneered the development of the VLSI design industry in the APAC region in 1984.
  • Created the feature dialer series of ASICs, winning over AT&T Consumer Products as a major customer in 1988.
  • Trained and helped Fujitsu designers successfully designed the mixed signal laser driver chip, winning over Fujitsu, Japan.
  • Successfully took over the design and support of all RAMDAC products, mainly for Apple MAC computers.
  • Successfully took over the design and support of all 10BaseT PHY products.
  • Successfully took over the design and support of all Ethernet 100VG (with HP Roseville), and later the 100BaseT products.
  • Successfully completed 0.9 m cmos design and process technology transfer to Hua Tsing Semiconductor, China in 1995/6 (Chinese 908 Project).
  • Oversaw the complete design of the NAS (Network Attached Storage) series of products using teams from Allentown PA, Singapore, Shanghai and India, 2004-2006.
  • Oversaw the design verification and field application support of Agere's Network Processors.
  • Designs span over CMOS technologies ranging from 3.5um to 0.065um.
  • Chip scales ranged from ~10k gates to > 10M gates (>40 Million transistors) SOCs.
Marketing
  • Won the feature dialer series of product (12 asics) from AT&T Consumer Products, building it into a major account.
  • Won the first few asics from Seagate, went on to design 12 more asics (with 100% first time success rate), resulting in Seagate being the biggest customer (with annual revenue of between $300M to $500M) with Agere Systems and the creation of the Storage BU.
  • Won the first 8 wireless asics designs (executed with 100% first success) from Samsung, Korea, resulting in Samsung being the biggest Mobility business customer (with annual revenue around $300M) and the creation of the Mobility BU in Agere Systems; in winning these designs we came up against formidable competitors the likes of TI, LSI, NEC, Fujitsu, and Samsung Microelectronics.
  • Successfully broke into Huawei and ZTE asic business in China, winning over from long entrenched, strong competitors like TI, IBM, STW and LSI.
Management
  • Established design centers in Singapore, Taipei, Hsinchu, Tokyo, Seoul and Shanghai.
  • Experienced in the winding up of Honeywell-Synertec and repackaging ourselves and going on roadshows to sell the operation to the eventual buyer, AT&T.
  • Experienced in, operating as a remote design center, the constant need to win projects, to keep relevance, and the struggle for recognition. Success in the form of the conferment of Bell Labs status by Dr. Ian Ross, President of AT&T Bell Labs, 1990, the only full indigenously staffed Bell Labs outside the USA.
  • Managed more than 70 high power R&D staff over several centers in the region with high productivity, delivery to commitment, and at an extremely low turnover rate.
  • As the VP & GM, established the Digital Media Business Unit in Huahong International in a very short time of less than 6 months.
  • Experienced in successful technology partnership agreement with IBM and other IP vendors.
  • Experienced in merger and acquisition negotiations, due diligence, and execution.
  • Participated in high stake negotiations with big equity investors like Silver Lakes, Blackstones and Carlyle.
  • Consulting for startups and providing guidance and assistance in venture funding.
Research Interests
  • Multicore embedded systems
  • Fast memory access systems
  • Network Processing and traffic management
  • Digital Multimedia systems
Awards & Honours
  • Adjunct Associate Professor, Nanyang Technological University, Singapore, 1987-2005.
  • Member International Advisory Committee, International Symposium on IC Design, Manufacturing and Applications: NTU, IEEE, IEE, 1995-2005.
  • Member Academic Advisory Committee, Singapore Polytechnic, Singapore, 1888-2003.
  • British Council Fellowship, Imperial College, London, 1982.
  • Lecturer/Instructor, Associate Member, International College for Microprocessors and Applications, International Centre for Theoretical Physics, IAEA, United Nations University, 1981-1995.
  • Associate Member, International Centre for Theoretical Physics (ICTP), Trieste, 1977-1979.
  • Nuffield Foundation Fellowship, University College, University of London, 1977.
  • Federal Scholarship Malaysia, University Malaya, Kuala Lumpur, 1968-1971.

Selected Publications
  • Twenty-six publications and conference papers.
Professional Membership
  • Fellow, Institute of Physics, Malaysia, 1973-2007.
  • Member, IEE, United Kingdom, 1983-2008.
  • Member, IEEE, USA, 1984-2008.

Quarterly Activites
September - December 2009
  • Meeting with FES and FEGT staff on VLSI curriculum, 2-Sep-09, 10:00am - 12:00pm, UTAR Kampar
    • Participant: FES and FEGT staff
    • Outcome: Some suggestions on curriculum improvement have been made
  • Meeting with USAINS Group on possible collaboration in curriculum and R&D, 26-Nov-09, 2:00pm - 4:00pm in UTAR PJ
    • Participant: VP (RDC), UTAR, USAINS Group
March - August 2009
  • Discussion on Possible Research and Training Activities in VLSI with Lee Sze Wei, Lim Soo King, Wang Chan Chin, 5-Feb-09
    • Outcome: The discussion ended with a plan for CM Tang to visit FES and FSET for meetings and discussions with relevant faculty staff
  • Talk titled "Ten Generations of Process Technology in 20 Years - A Designer's Odyssey" was delivered by CM Tang at FES, UTAR, 15-Apr-09, 2pm
    • Outcome: The talk and Q&A session were beneficial to the student and academic community in UTAR as far as industry practices and trends are concerned
  • Dialog session with relevant staff of FES, Dept of Electrical and Electronic Engineering, FES, 15-Apr-09, 4pm.
    • Outcome: CM Tang was given an overview of the currciculum of Bachelor of Engineering (Hons) Electrical and Electronic Engineering and Bachelor of Engineering (Hons) Electronic and Communications Engineering.
    • Discussion of skill expectation of industry on electronic engineering graduates was held and some ideas of addressing such needs in curriculum were also discussed.
  • Appointment of CM Tang as Faculty Industrial Advisor (FSET ' FEGT), 1-Apr-09.
April - June 2010
  • Setting up of VLSI lab in UTAR Kampar, ongoing, UTAR Kampar
    • Participant: FES and FEGT staff
    • Outcome: Providing advice on the setup of the lab
  • Planning training for staff of UTAR teaching VLSI subjects, ongoing, UTAR Kampar
    • Participant: FES and FEGT staff
    • Outcome: Being the trainer for the programme to start in Sep 2010
  • Chairing of VLSI centre of UTAR, ongoing, UTAR Kampar & KL
    • Participant: FES and FEGT staff
July - September 2010
  • Conducting series of VLSI training
  • Planning to start a VLSI design project
  • Chairing of VLSI centre of UTAR
  • Meeting with industry collaborators e.g. Intel & Infineon
October - December 2010
  • Conducting series of VLSI training in UTAR Kampar, currently focusing on design project based training.
  • Chairing of UTAR VLSI centre
  • Preparing for the first subject in VLSI to be introduced in FEGT in UTAR Kampar
January - March 2011
  • Conducting series of VLSI training for staff from FES and FEGT(Ongoing). Currently focusing on design project based training.
  • Chairing of VLSI centre of UTAR (Ongoing).
  • Preparing for the second subject in VLSI to be introduced in FEGT (Ongoing).
April - June 2011
  • Conducting series of VLSI training
  • Chairing of VLSI centre of UTAR
  • Doing minor revision to VLSI subject content
July - September 2011
  • Conducting series of VLSI training for FEGT staff. Currently focusing on design project based training (On-going)
  • Chairing of VLSI Centre of UTAR (On-going)
  • Doing minor revision to VLSI subject content (On-going)
  • Guiding postgraduate candidates (On-going)
October - December 2011
  • Conducting series of VLSI training for FEGT staff. Currently focusing on design project based training (On-going)
  • Chairing of VLSI Centre of UTAR (On-going)
  • Guiding postgraduate candidates (On-going)
January - March 2012
  • Conducting series of VLSI training for FEGT staff. Currently focusing on design project based training (On-going)
  • Chairing of VLSI Centre of UTAR (On-going)
  • Guiding postgraduate candidates (On-going). Currently, two postgraduates undergoing training at CM Tang's office in Shanghai (Feb - Mar 2012). CM Tang has given a talk on 30th January, 2012, 2pm. The title of his talk is "A New Dimension in VLSI Design".
  • He is currently the external consultant for a postgraduate student who has registered his Master's studies with FEGT.
April - June 2012
  • Conducting series of VLSI training for FEGT staff. Currently focusing on design project based training (On-going)
  • Chairing of VLSI Centre of UTAR (On-going)
  • Guiding postgraduate candidates (On-going). Currently, two postgraduates undergoing training at CM Tang's office in Shanghai (Feb - Mar 2012). CM Tang has given a talk on 30th January, 2012, 2pm. The title of his talk is "A New Dimension in VLSI Design".
  • He is currently the external consultant for a postgraduate student who has registered his Master's studies with FEGT.
July - September 2012 To be part of the examining committee for proposal defences by MEngSc candidates, Mr Lim Zhen Ning and Mr Dicky Hartono
October - December 2012
  • Chairing of VLSI centre of UTAR
  • Guiding postgraduate candidates (Currently, two postgraduates under co-supervision of CM Tang)
  • Regular visit and meeting at UTAR ( Regular meetings with research postgraduates)
January - March 2013
  • Meeting and discussion with postgraduate students at least once a week through Skype
  • Will be visiting UTAR on 1st & 2nd April 2013
  • Has started the new cycle of UTARRF project.
April - June 2013
  • Training of master postgraduates on VLSI
  • VLSI research project to develop very low power multi-core processor
July - September 2013
  • Continue to guide and supervise 3 master postgraduates in VLSI.
  • Help to recruit one more postgraduate in VLSI in Oct 2013
  • Will present papers together with master postgraduates in a conference in Indonesia and now in process of preparing the papers.
  • Hosted the students for industrial attachment in Shanghai, May - Sep 2013.
October - December 2013
  • Presented 3 conference papers in Indonesia together with the three postgraduates under his supervision.
  • Hosted one postgraduate for industrial attachment in Shanghai.
January - March 2014
  • Visited UTAR Kampar: Feb 2014
  • Continuing the supervision of 4 master postgraduates in VLSI
  • Awarded an UTARRF for a VLSI project in Cycle 2, 2013 - project commenced in Jan 2014
April - June 2014
  • Continue the supervision of 4 postgraduates in VLSI as FEGT.
  • Chairing of VLSI centre
  • Preparing the final stage of taping out the multi-core processor design for IC fabrication
July - September 2014
  • Chairing of VLSI RC
  • Supervising master postgraduates in FEGT.
  • PI for UTARRF projects
October - December 2014
  • Attended the BOE / viva for a master postgraduate
  • Conducted RC meeting
  • Conducted presentation on future direction and research focus of RC
January - March 2015
  • 1 master student graduated with MEngSc at FEGT.
  • Recruited a new master student for VLSI research.
  • Visited FEGT on 27 Feb 2015
April - June 2015
  • 2015 VLSI Seminar
  • Supervision of final year project
July - September 2015
  • Final Year Project Assessment
  • Proposal Defense
  • Final Year Project Supervision
  • Informal dialogue session
  • Postgraduate Supervision
October - December 2015
  • No activity reported for this quarter.
January - March 2016
  • Work Completion Seminar - Mr. Arya Wicaksana
  • Appointment of internal examiner for Arya Wicaksana
  • Appointment of internal examiner for Felix Lokananta
  • Board of Examination Viva-voce (BoE Viva) for Felix Lokananta
  • Postgraduate and undergraduate final year project supervision
  • Price commitment from Cadence for UTAR
April - June 2016
  • Board of Examiners Meeting (for the Examination of Dissertation)
July - September 2016
  • ICP meeting with Prof. Lee and Silterra.
  • CVLSIR meeting
  • Assessment of Master of Science by research student dissertation submission
October - December 2016
  • Industry-University Link Forum
  • Launch of the RUMPS401
  • Centre meeting
  • Member of Centre of Very Large Scale Integration Research meeting Vice President (R&D and Commercialization)
  • Technical Seminar and Workshop Series
January - March 2017
  • Centre meeting on 9 March 2017
  • Renewal of ICP was submitted on 11 Jan 2017
April - June 2017
  • 1. Welcoming new member to CVLSIR : Dr. Soh Chit Siang
  • 2. Welcoming new member to CVLSIR : Mr. Yang Chuan Choong
  • 3. UTARRF 2017 Cycle 1: Project Number IPSR/RMC/UTARRF/2017-C1/T03. Funding for a new project "Extreme low power encription decryption unit for IoT"
July - September 2017
  • Centre for Very Large Scale Integration Research meeting
  • "UTARRF 2017 Cycle 1:
  • Project Number IPSR/RMC/UTARRF/2017-C1/T03"
  • Request by ARM to have some information on UTAR RUMPS401 chip
  • Registration of Master of Engineering Science student: Electronic System Level Virtual Platforming Design for Hardware and Software Co-design of a Secure System for Intelligent Internet of Things
  • Registration of Master of Engineering Science student: Hardware and Software Co-development for a Secure and Intelligent Internet of Things System
  • WCS conducted in FEGT: Design of Software Defined Radio-based RF Transceiver for IoT in Multi-Processor System On Chip - a Preliminary Review.
October - December 2017
  • VLSI Research centre meeting was held on Wednesday, 29 November 2017, 4 pm in E018A, VLSI Design Lab. Mr. CM Tang and Dr. Yap V. V. visited Universitas Multimedia Nusantara Jakarta on 1 December 2017 to attend the university's convoction.
  • The Master of Engineering Science students' application for VISA was finally approved. One student arrived on 6 November 2017, and the other arrived on 25 November 2017. Mr. CM Tang's visit to welcome these two students closed the day with dinner in a restaurant.
January - March 2018
  • The two postgraduates spent the CNY break with Mr. CM Tang in Kuala Lumpur. Basically the students are making good progress getting up to speed with using the RUMPS401.
April - June 2018
  • Attended CVLSI meeting on 24 May 2018
  • Attended proposal defence for Vincentius Kurniawan on 24 May 2018
  • Visited GLX Technologies Sdn Bhd with Dicky Hartono, Lim Zhen Ning, and two other member of staff of GL on 23 May 2018
  • Synopsys licensing - CM Tang has agreement from Wong of ICE that Synopsys licensing to have back-end and front-end licenses double up if only BE or FE licenses are used. He has also negotiated for the licenses in Kampar to be shared by Sungai Long. This arrangement requires ITISC to setup dedicated port for access to licenses in the server in Kampar.